I. Field of the Invention
This invention relates to a method of manufacturing a semiconductor memory device which has a memory cell structure consisting of one transistor and one capacitor, and which stores data by way of electrical charges retained in the capacitor.
II. Description of the Prior Art
The memory cell of a dynamic RAM (dRAM) generally comprises an MOS capacitor which retains data in the form of an electrical charge, and a switching MOS transistor which exchanges the charge with an external circuit. As a dRAM increases in its memory capacity, each memory cell has to be progressively reduced in area. However, since the level of a signal for the reading of data is determined by the amount of charge stored in the MOS capacitor, its effective area cannot be reduced significantly. Up until the present time, therefore, a large number of proposals have been put forward which are designed to form a groove in the semiconductor substrate and provide a capacitor therein in three-dimensional form, in order to reduce the area of a capacitor provided on a chip and, while preserve a large effective area of the capacitor.
From the point of view of the fabricating technique, however, it is difficult to form a fine deep groove in a substrate. An MOS transistor constituting another structural element of a memory cell has to be miniaturized to permit the high integration of the subject semiconductor memory device. However, attempts to unduly shorten the gate length, to aid in the miniaturization of the subject device, incur the drawback in that the reliability of the device will be reduced because of, for example, the hot carrier effect.
Furthermore, demand for the high integration of a dRAM and the miniaturization of semiconductor elements has given rise to the under-mentioned difficulties. The structural elements such as a transistor and capacitor decrease in length, but not in thickness. Consequently, the aspect ratio of the respective layers increases. When, for example, a contact hole is formed by photolithography, the standing wave effect occurring in the stepped portion reduces the dimensional precision and gives rise to etching residues. When an interconnection layer is formed, disconnection and other difficulties arise at the time of deposition.
As has been described above, the high integration of a dRAM and the miniaturization of the elements involved are accompanied with various difficulties. The most important of the above-mentioned problems which most urgently require resolution are the elimination of the alignment margin between the capacitor and transistor as well as that between the bit line contact hole and transistor, and the achieving of a substrate having perfect flatness.